A current mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders

Q4 Arts and Humanities Czas Kultury Pub Date : 2003-12-14 DOI:10.1109/ICECS.2003.1301962
S. Hemati, A. Banihashemi
{"title":"A current mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders","authors":"S. Hemati, A. Banihashemi","doi":"10.1109/ICECS.2003.1301962","DOIUrl":null,"url":null,"abstract":"A new current-mode maximum winner-take-all (max WTA) circuit is presented. Inputs and output of the circuit are high swing, and voltage requirements for the inputs and the output are very low and just about V/sub eff/ (V/sub sat/) and 2 V/sub eff/ (2 V/sub sat/), respectively. Because of the cascode configuration, the proposed circuit shows very good precision even for short channel MOSFETs. Simulation results based on 0.13 /spl mu/m UMC CMOS technology are also presented. These results demonstrate the high-precision and low-voltage requirement of the circuit, which makes it a good choice for low-voltage min-sum analog iterative decoders and other soft computing applications.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"57 10 1","pages":"4-7 Vol.1"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Czas Kultury","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2003.1301962","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Arts and Humanities","Score":null,"Total":0}
引用次数: 6

Abstract

A new current-mode maximum winner-take-all (max WTA) circuit is presented. Inputs and output of the circuit are high swing, and voltage requirements for the inputs and the output are very low and just about V/sub eff/ (V/sub sat/) and 2 V/sub eff/ (2 V/sub sat/), respectively. Because of the cascode configuration, the proposed circuit shows very good precision even for short channel MOSFETs. Simulation results based on 0.13 /spl mu/m UMC CMOS technology are also presented. These results demonstrate the high-precision and low-voltage requirement of the circuit, which makes it a good choice for low-voltage min-sum analog iterative decoders and other soft computing applications.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
一种用于最小和模拟迭代解码器的低电压电流模式最大赢家通吃电路
提出了一种新的电流模式最大赢家通吃电路。电路的输入和输出为高摆幅,输入和输出的电压要求非常低,分别约为V/sub / (V/sub sat/)和2v /sub / (2v /sub sat/)。由于级联码结构,即使对于短沟道mosfet,所提出的电路也显示出非常好的精度。并给出了基于0.13 /spl mu/m UMC CMOS技术的仿真结果。这些结果证明了该电路的高精度和低电压要求,使其成为低压最小和模拟迭代解码器和其他软计算应用的理想选择。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
Czas Kultury
Czas Kultury Social Sciences-Social Sciences (miscellaneous)
CiteScore
0.10
自引率
0.00%
发文量
10
期刊最新文献
Aktywizm dający przyjemność: działanie na zasadzie wspólnej zgody, lokalne zakorzenienie i oddolne polityki integracyjne Ekopareneza. Rozpoznania wstępne Paradoks Kasztanki. Fantazmatyczne eksponaty w domach-muzeach Luzowanie ontologii. O wytwarzaniu więcej-niż-ludzkich lokalności na Górnym Śląsku Przez negantropologię do obywatelskiej rewolucji w lokalnościach
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1