Predictive Power Control Circuit Model With T-DET-FF for Hybrid Pulsed Latch Implementation

Abstract

Pulsed Latches circuits are one important aspects of the reduction of power for each read and write operations in memories. As the design complexity with reduction of nanometers increases the design analysis on power and other performance factors with relate to foundry techniques encapsulated in Semiconductor gates. With importance of low power feature in memories are implied with reduction of size of the transistor and its implementation with type of application chosen. In this paper, we implicate on the feature of power reduction models with a hybrid feature of T-DET-FF modelling with PPC circuit design using transistor gates. With regards of the power and the transistor size the proposed algorithm sufficiently provides the values W/L ratio to implicate the different conditions for Pulsed latches for memory write and read conditions. The simulated results with D-T-FF are implicated with Dynamic CMOS latch with PPC circuit as the comparison of different foundries with 32nm, 45nm and 65nm