Increasing the speed and reducing a sensing delay of content addressable memory

Abstract

High speed content addressable memory design has high speed search function in a single clock. Parallel match line is used to compare. In robust Low power sense amplifier and high speed are highly sought-after in CAM designs. The value is given to search engine and its finds the value where its present. In the existing parity bit is introduced that leads to delay reduction at a cost of less than area. Furthermost in the proposed system PMOS transistor is used and cascaded and then output is found. Deadline is used in the proposed system to identify if the value is not present in the system.