Design and Fabrication of Planar Schottky Diode for Electrostatic Discharge Protection

Chong Shen, Xiu-Lan Cheng
{"title":"Design and Fabrication of Planar Schottky Diode for Electrostatic Discharge Protection","authors":"Chong Shen, Xiu-Lan Cheng","doi":"10.12783/dteees/peems2019/33984","DOIUrl":null,"url":null,"abstract":"A type of easy-to-fabricate Schottky diode with controllable breakdown voltage is design and fabricated. The Schottky junction is formed by the contact of Aluminum electrode and light doped n-type silicon. A special comb teeth structure is designed to lower the resistance and breakdown voltage. The diodes can achieve breakdown voltage between 2V and 16V by optimizing the doping concentration of the substrate and the distance of the comb teeth. The diode has great application potential in electro-static discharge (ESD) protection circuit, due to its easy compatibility in CMOS circuit process and ability of withstanding high currents. Introduction With the development of semiconductor technology, the IC devices are scaling down, achieving higher device density and faster working frequency. However, the damage that comes with electro-static discharge (ESD) are becoming increasingly significant [1,2]. This makes developing ESD protection devices that are compatible with IC fabrication devices a necessity. Many kinds of devices can be used as ESD protection devices, including Zener diode [3,4] and transient voltage suppressor (TVS) [5,6], etc. They are both variants of PN junction diode. Schottky diode is another option for ESD protection [7,8]. Schottky diode uses certain metal materials, such as gold, silver, aluminum and platinum, as anode, and uses n-type semiconductor as cathode. The contact of these materials produces rectification property. Schottky diode has two major differences: magnitude of reverse saturation current and switching characteristic when compared with PN junction diodes, The reverse current density of a Schottky diode can be calculated from equation (1) while that of an ideal PN junction can be calculated from equation (2). JsT = A T exp (− eΦBn kT ) (1) Js = eDnnp0 Ln + eDppn0 Lp (2) In equation (1), e is the charge of an electron, A * is effective Richardson’s constant, φBn is the height of Schottky barrier, k is Boltzmann constant and T is the temperature (Kelvin). In equation (2), Dn and Dp are diffusion coefficient of minority electrons and holes, whose diffusion length is noted as Ln and Lp. np0 and pn0 are minority electron and hole density under heat balance. The transport mechanism of Schottky diode and PN junction diode is different, for the two equations above exhibit different forms. The current in PN junction is mainly determined by the diffusion of minority carrier, whereas that in Schottky junction is mainly determined by thermionic emission of majority carrier. With the same substrate doping concentration, it can be found that the reverse saturation current of Schottky diode is several magnitudes larger than that of PN junction diode. Another major difference between Schottky diode and PN junction diode is their switching speed. As a device whose current is mainly produced by majority carrier, the switching time of Schottky diode is magnitudes smaller than that of PN junction diode, whose current is mainly produced by minority carrier [9] . Typical fabrication process of Schottky diode uses a vertical structure [10,11], the two electrodes are on the different side of the chip. Epitaxy process is also used, as is shown in Figure.1. Vertical structure takes lager space in the circuit and cannot be integrated into CMOS chips. The precise breakdown voltage control is more difficult in this structure as well. Figure 1. Typical structure of Schottky diode. Therefore, a special planar comb structure of Schottky diode is proposed in this paper to achieve easy integration on a single chip. Moreover, the breakdown voltage of the device can be easily controlled by adjusting the distance of the comb teeth. At the same time, the fabrication cost can be lowered for there is no epitaxy process. Design and Fabrication A comb-shaped structure has been employed in order to decrease the series resistance of the diode and improve its performance [12]. The length of the contact area is noted as L, width as w and the distance of two contact area as d. The top view of the structure is shown in Figure.2. Figure 2. The top view of the Schottky diode. The vertical profile of the Schottky diode is shown in Figure.3. The device consists of an n substrate, a heavy doped area, a SiO2 layer and metal electrodes. Figure 3. Vertical profile of the Schottky diode. Figure 4. Flow chart of the fabrication process. Figure 5. Photo of fabricated device. Two different types of 4-inch n-type <100> wafers are chosen for the fabrication. One has a doping concentration of 5×10 13 cm -3 and a thickness of 525um and another has a doping concentration of 1×10 16 cm -3 and a thickness of 525um. The first step is to clean the surface of the wafer with acetone and isopropanol, then deposit a 250nm-thick SiO2 layer with plasma enhanced chemical vapor deposition (PECVD). The SiO2 layer is etched to form the area for Schottky diodes and the marks for following alignments with Reactive Ion Etching (RIE). After that, remove the photoresist with acetone cleaning and plasma strip. Ion-implantation at the energy of 15 keV and with the dose of 5×10 14 cm -2 is performed to form heavy doped area, whose target concentration is 10 20 ~10 21 cm -3 . Rapid thermal process (RTP) is performed under 1030°C for 8 seconds to activate the dopants. Then, deposit another 200nm-thick layer of SiO2 with PECVD and form the contact area for the diodes with lithography and etching. This layer of oxide can protect the diodes and reduce the edge electric field, thus decrease the leakage current and improve the diodes’ breakdown performance. Then fabricate the electrodes with Aluminum and form the pad pattern with lift-off process. Before this step, the wafer is cleaned with BOE (Buffered Oxide Etch) for 15 seconds to remove potential natural oxide layer. After the fabrication, anneal the wafer for 10 minutes under 475°C and N2 atmosphere to form good ohmic and Schottky contact. The whole process is shown in Figure.4 and the photos of the fabricated devices are shown Figure.5. The I-V curve of the fabricated Schottky diodes is tested by Agilent BA-1500 semiconductor parameter tester equipped with a probe station. The voltage applied on the diode sweeps from 0V to 18V by the step of 0.18V, there are 100 steps in total. The current through the diode is measured and plotted. Results and Discussions The I-V curves of fabricated Schottky diodes with different electrode distance are shown in Figure.6. The curve ends at 100mA current because the maximum scale of the tester is reached. Figure.7 shows the relationship between the breakdown voltage and the distance of the electrodes, namely the parameter d. Figure 6. I-V curve of the Schottky diode (Substrate doping concentration: 1×10 16 cm -3 ). Figure 7. Breakdown voltage of the Schottky diode at different distances of the electrodes. Effect of Doping Concentration of the Substrate on the Breakdown Voltage Figure.7 shows that under the same electrode distance, higher doping concentration of the substrate can achieve lower breakdown voltage. This can be explained by the avalanche break down mechanism of the Schottky diode. When metal and n-type semiconductor contacts each other, a space charge region is formed, whose width W can be calculated with equation (3): W = [ 2εs(Vbi+VR) eNd ] 1 2 (3) where εs is the dielectric constant of Silicon, Nd is the doping concentration of the substrate, and Vbi and VR are the diode’s built-in potential and reverse bias applied respectively. Reverse biased, the carriers will start to move due to the electric field. When the electric field is strong enough (critical electric field strength, Ecrit, related to the condition of the substrate), the mobile carriers can be accelerated to high enough speed to activate other bound electrons, which results in higher current and more electron activations, namely the breakdown phenomenon. When regarded as an abrupt junction, the breakdown voltage BV of a Schottky junction can be calculated by equation below [13]:","PeriodicalId":11369,"journal":{"name":"DEStech Transactions on Environment, Energy and Earth Science","volume":"12 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"DEStech Transactions on Environment, Energy and Earth Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.12783/dteees/peems2019/33984","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

A type of easy-to-fabricate Schottky diode with controllable breakdown voltage is design and fabricated. The Schottky junction is formed by the contact of Aluminum electrode and light doped n-type silicon. A special comb teeth structure is designed to lower the resistance and breakdown voltage. The diodes can achieve breakdown voltage between 2V and 16V by optimizing the doping concentration of the substrate and the distance of the comb teeth. The diode has great application potential in electro-static discharge (ESD) protection circuit, due to its easy compatibility in CMOS circuit process and ability of withstanding high currents. Introduction With the development of semiconductor technology, the IC devices are scaling down, achieving higher device density and faster working frequency. However, the damage that comes with electro-static discharge (ESD) are becoming increasingly significant [1,2]. This makes developing ESD protection devices that are compatible with IC fabrication devices a necessity. Many kinds of devices can be used as ESD protection devices, including Zener diode [3,4] and transient voltage suppressor (TVS) [5,6], etc. They are both variants of PN junction diode. Schottky diode is another option for ESD protection [7,8]. Schottky diode uses certain metal materials, such as gold, silver, aluminum and platinum, as anode, and uses n-type semiconductor as cathode. The contact of these materials produces rectification property. Schottky diode has two major differences: magnitude of reverse saturation current and switching characteristic when compared with PN junction diodes, The reverse current density of a Schottky diode can be calculated from equation (1) while that of an ideal PN junction can be calculated from equation (2). JsT = A T exp (− eΦBn kT ) (1) Js = eDnnp0 Ln + eDppn0 Lp (2) In equation (1), e is the charge of an electron, A * is effective Richardson’s constant, φBn is the height of Schottky barrier, k is Boltzmann constant and T is the temperature (Kelvin). In equation (2), Dn and Dp are diffusion coefficient of minority electrons and holes, whose diffusion length is noted as Ln and Lp. np0 and pn0 are minority electron and hole density under heat balance. The transport mechanism of Schottky diode and PN junction diode is different, for the two equations above exhibit different forms. The current in PN junction is mainly determined by the diffusion of minority carrier, whereas that in Schottky junction is mainly determined by thermionic emission of majority carrier. With the same substrate doping concentration, it can be found that the reverse saturation current of Schottky diode is several magnitudes larger than that of PN junction diode. Another major difference between Schottky diode and PN junction diode is their switching speed. As a device whose current is mainly produced by majority carrier, the switching time of Schottky diode is magnitudes smaller than that of PN junction diode, whose current is mainly produced by minority carrier [9] . Typical fabrication process of Schottky diode uses a vertical structure [10,11], the two electrodes are on the different side of the chip. Epitaxy process is also used, as is shown in Figure.1. Vertical structure takes lager space in the circuit and cannot be integrated into CMOS chips. The precise breakdown voltage control is more difficult in this structure as well. Figure 1. Typical structure of Schottky diode. Therefore, a special planar comb structure of Schottky diode is proposed in this paper to achieve easy integration on a single chip. Moreover, the breakdown voltage of the device can be easily controlled by adjusting the distance of the comb teeth. At the same time, the fabrication cost can be lowered for there is no epitaxy process. Design and Fabrication A comb-shaped structure has been employed in order to decrease the series resistance of the diode and improve its performance [12]. The length of the contact area is noted as L, width as w and the distance of two contact area as d. The top view of the structure is shown in Figure.2. Figure 2. The top view of the Schottky diode. The vertical profile of the Schottky diode is shown in Figure.3. The device consists of an n substrate, a heavy doped area, a SiO2 layer and metal electrodes. Figure 3. Vertical profile of the Schottky diode. Figure 4. Flow chart of the fabrication process. Figure 5. Photo of fabricated device. Two different types of 4-inch n-type <100> wafers are chosen for the fabrication. One has a doping concentration of 5×10 13 cm -3 and a thickness of 525um and another has a doping concentration of 1×10 16 cm -3 and a thickness of 525um. The first step is to clean the surface of the wafer with acetone and isopropanol, then deposit a 250nm-thick SiO2 layer with plasma enhanced chemical vapor deposition (PECVD). The SiO2 layer is etched to form the area for Schottky diodes and the marks for following alignments with Reactive Ion Etching (RIE). After that, remove the photoresist with acetone cleaning and plasma strip. Ion-implantation at the energy of 15 keV and with the dose of 5×10 14 cm -2 is performed to form heavy doped area, whose target concentration is 10 20 ~10 21 cm -3 . Rapid thermal process (RTP) is performed under 1030°C for 8 seconds to activate the dopants. Then, deposit another 200nm-thick layer of SiO2 with PECVD and form the contact area for the diodes with lithography and etching. This layer of oxide can protect the diodes and reduce the edge electric field, thus decrease the leakage current and improve the diodes’ breakdown performance. Then fabricate the electrodes with Aluminum and form the pad pattern with lift-off process. Before this step, the wafer is cleaned with BOE (Buffered Oxide Etch) for 15 seconds to remove potential natural oxide layer. After the fabrication, anneal the wafer for 10 minutes under 475°C and N2 atmosphere to form good ohmic and Schottky contact. The whole process is shown in Figure.4 and the photos of the fabricated devices are shown Figure.5. The I-V curve of the fabricated Schottky diodes is tested by Agilent BA-1500 semiconductor parameter tester equipped with a probe station. The voltage applied on the diode sweeps from 0V to 18V by the step of 0.18V, there are 100 steps in total. The current through the diode is measured and plotted. Results and Discussions The I-V curves of fabricated Schottky diodes with different electrode distance are shown in Figure.6. The curve ends at 100mA current because the maximum scale of the tester is reached. Figure.7 shows the relationship between the breakdown voltage and the distance of the electrodes, namely the parameter d. Figure 6. I-V curve of the Schottky diode (Substrate doping concentration: 1×10 16 cm -3 ). Figure 7. Breakdown voltage of the Schottky diode at different distances of the electrodes. Effect of Doping Concentration of the Substrate on the Breakdown Voltage Figure.7 shows that under the same electrode distance, higher doping concentration of the substrate can achieve lower breakdown voltage. This can be explained by the avalanche break down mechanism of the Schottky diode. When metal and n-type semiconductor contacts each other, a space charge region is formed, whose width W can be calculated with equation (3): W = [ 2εs(Vbi+VR) eNd ] 1 2 (3) where εs is the dielectric constant of Silicon, Nd is the doping concentration of the substrate, and Vbi and VR are the diode’s built-in potential and reverse bias applied respectively. Reverse biased, the carriers will start to move due to the electric field. When the electric field is strong enough (critical electric field strength, Ecrit, related to the condition of the substrate), the mobile carriers can be accelerated to high enough speed to activate other bound electrons, which results in higher current and more electron activations, namely the breakdown phenomenon. When regarded as an abrupt junction, the breakdown voltage BV of a Schottky junction can be calculated by equation below [13]:
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静电放电保护用平面肖特基二极管的设计与制造
设计并制作了一种易于制作的击穿电压可控肖特基二极管。通过铝电极与掺光n型硅的接触形成肖特基结。特殊的梳齿结构设计,降低电阻和击穿电压。通过优化衬底掺杂浓度和梳齿距离,二极管击穿电压可达到2V ~ 16V。该二极管具有易于兼容CMOS电路工艺和耐大电流的特点,在静电放电保护电路中具有很大的应用潜力。随着半导体技术的发展,集成电路器件的小型化,器件密度越来越高,工作频率越来越快。然而,静电放电(ESD)带来的损害越来越严重[1,2]。这使得开发与IC制造设备兼容的ESD保护器件成为必要。多种器件可作为ESD保护器件,包括齐纳二极管[3,4]和瞬态电压抑制器(TVS)[5,6]等。它们都是PN结二极管的变体。肖特基二极管是ESD保护的另一个选择[7,8]。肖特基二极管以金、银、铝、铂等一定的金属材料为阳极,以n型半导体为阴极。这些材料的接触产生整流性能。肖特基二极管有两个主要区别:级反向饱和电流和开关特性与PN结二极管相比,肖特基二极管的反向电流密度可以计算从方程(1)的一个理想的PN结可以计算从方程(2),JsT = T exp(−eΦBn kT) (1) Js = eDnnp0 Ln + eDppn0 Lp在方程(1)(2),e是电子的电荷,*是有效的理查森的常数,φBn肖特基势垒的高度,k是玻尔兹曼常数,T是温度(开尔文)式(2)中,Dn和Dp为少数电子和空穴的扩散系数,其扩散长度记为Ln和Lp。Np0和pn0为热平衡下的少数电子和空穴密度。肖特基二极管和PN结二极管的输运机制是不同的,因为上述两种方程的形式不同。PN结的电流主要由少数载流子的扩散决定,而肖特基结的电流主要由多数载流子的热离子发射决定。在衬底掺杂浓度相同的情况下,肖特基二极管的反向饱和电流比PN结二极管的反向饱和电流大几个数量级。肖特基二极管和PN结二极管的另一个主要区别是它们的开关速度。肖特基二极管作为主要由多数载流子产生电流的器件,其开关时间比主要由少数载流子产生电流的PN结二极管的开关时间要小几个数量级[9]。肖特基二极管的典型制造工艺采用垂直结构[10,11],两个电极位于芯片的不同侧面。还采用了外延工艺,如图1所示。垂直结构在电路中占用较大空间,不能集成到CMOS芯片中。在这种结构中,精确的击穿电压控制也比较困难。图1所示。肖特基二极管的典型结构。为此,本文提出了一种特殊的平面梳状肖特基二极管结构,使其易于在单芯片上集成。而且,通过调整梳齿的距离,可以很容易地控制装置的击穿电压。同时,由于没有外延工艺,可以降低制造成本。为了减小二极管的串联电阻,提高二极管的性能,采用了梳状结构[12]。接触区域的长度记为L,宽度记为w,两个接触区域的距离记为d。结构俯视图如图2所示。图2。肖特基二极管的俯视图。肖特基二极管的垂直轮廓如图3所示。该器件由n衬底、重掺杂区、SiO2层和金属电极组成。图3。肖特基二极管的垂直轮廓。图4。制作工艺流程图。图5。制作的器件照片。选择了两种不同类型的4英寸n型晶圆进行制造。一个掺杂浓度为5×10 13 cm -3,厚度为525um,另一个掺杂浓度为1×10 16 cm -3,厚度为525um。第一步是用丙酮和异丙醇清洗晶圆表面,然后用等离子体增强化学气相沉积(PECVD)沉积250nm厚的SiO2层。SiO2层被蚀刻以形成肖特基二极管的区域和反应离子蚀刻(RIE)后续对准的标记。
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