{"title":"A novel scheme for testing radio frequency voltage controlled oscillators","authors":"L. Dermentzoglou, Y. Tsiatouhas, A. Arapoyanni","doi":"10.1109/ICECS.2003.1301855","DOIUrl":null,"url":null,"abstract":"In this paper, a novel scheme for testing LC-tank CMOS Voltage Controlled Oscillators (VCOs) is presented. The proposed test circuit is capable of detecting soft and hard faults in a percentage that can guarantee safe overall fault coverage. It has been realized that the proposed technique is capable of detecting open and short circuits as well as process variations outside the specified limits in the passive components of the VCO in a percentage that exceeds 93%. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit, which additionally presents negligible silicon area requirements in the design process.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"9 1","pages":"595-598 Vol.2"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Czas Kultury","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2003.1301855","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Arts and Humanities","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, a novel scheme for testing LC-tank CMOS Voltage Controlled Oscillators (VCOs) is presented. The proposed test circuit is capable of detecting soft and hard faults in a percentage that can guarantee safe overall fault coverage. It has been realized that the proposed technique is capable of detecting open and short circuits as well as process variations outside the specified limits in the passive components of the VCO in a percentage that exceeds 93%. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit, which additionally presents negligible silicon area requirements in the design process.
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