Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application

Abstract

A novel logic family, called Pipeline Event-driven No-race Charge recycling Logic (PENCL), has been proposed and analyzed. PENCL improves power efficiency using an event detector circuit. In this new logic, when an event is detected on the input signal, the outputs are connected. This technique theoretically reduces the power consumption 50% compared to conventional charge recycling logic. The efficiency of the new method was analyzed using seven 2-input NAND gates connected to each other as a pipeline modular structure. This configuration was simulated with 0.35/spl mu/m technology using HSPICE. Simulation results show 43% power reduction using this new method compared to one of the most power efficient charge-recycling logic called race-Free CMOS Pass gate Charge recycling Logic (FCPCL). Dual rail isolated latch (DRIL), which is introduced for using in PENCL, has much better performance than the previous static latch.