{"title":"MTPP - Modular Traffic Processing Platform","authors":"Jiri Halak, S. Ubik","doi":"10.1109/DDECS.2009.5012121","DOIUrl":null,"url":null,"abstract":"High-speed (10 Gb/s and above) network monitoring and traffic processing requires hardware acceleration. Different applications require different functions to be placed in hardware. Current packet capture cards include fixed firmware, which is difficult to extend. In this paper we propose an architecture for Modular Traffic Processing Platform (MTPP), which enables end users to easily modify hardware processing without any FPGA development. On the other hand, developers can create new processing modules with much reduced effort thanks to simple module interfaces and isolation of module time constraints.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"9 1","pages":"170-173"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2009.5012121","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
High-speed (10 Gb/s and above) network monitoring and traffic processing requires hardware acceleration. Different applications require different functions to be placed in hardware. Current packet capture cards include fixed firmware, which is difficult to extend. In this paper we propose an architecture for Modular Traffic Processing Platform (MTPP), which enables end users to easily modify hardware processing without any FPGA development. On the other hand, developers can create new processing modules with much reduced effort thanks to simple module interfaces and isolation of module time constraints.