A benchmark-based performance model for memory-bound HPC applications

B. Putigny, Brice Goglin, Denis Barthou
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引用次数: 15

Abstract

The increasing computation capability of servers comes with a dramatic increase of their complexity through many cores, multiple levels of caches and NUMA architectures. Exploiting the computing power is increasingly harder and programmers need ways to understand the performance behavior. We present an innovative approach for predicting the performance of memory-bound multi-threaded applications. It relies on micro-benchmarks and a compositional model, combining measures of micro-benchmarks in order to model larger codes. Our memory model takes into account cache sizes and cache coherence protocols, having a large impact on performance of multi-threaded codes. Applying this model to real world HPC kernels shows that it can predict their performance with good accuracy, helping taking optimization decisions to increase application's performance.
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一个基于基准的高性能计算应用程序的性能模型
随着服务器计算能力的不断增强,通过多核、多级缓存和NUMA架构,其复杂性也急剧增加。利用计算能力变得越来越困难,程序员需要理解性能行为的方法。我们提出了一种创新的方法来预测内存受限的多线程应用程序的性能。它依赖于微基准测试和组合模型,结合微基准测试的度量来模拟更大的代码。我们的内存模型考虑了缓存大小和缓存一致性协议,这对多线程代码的性能有很大的影响。将该模型应用于实际的高性能计算内核,结果表明,该模型能够较准确地预测高性能计算内核的性能,有助于做出优化决策以提高应用程序的性能。
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