B. Benbakhti, E. Towie, K. Kalna, G. Hellings, G. Eneman, K. De Meyer, M. Meuris, A. Asenov
{"title":"Monte Carlo analysis of In0.53Ga0.47as Implant-Free Quantum-Well device performance","authors":"B. Benbakhti, E. Towie, K. Kalna, G. Hellings, G. Eneman, K. De Meyer, M. Meuris, A. Asenov","doi":"10.1109/SNW.2010.5562589","DOIUrl":null,"url":null,"abstract":"III–V nMOSFETs are promising candidates for n-channel high-performance transistors in CMOS in the sub-22 nm technology [1]. High electron mobility and low effective mass resulting in a very high injection velocity and low backscattering promise high device performance [2] at a low supply voltage. Various high-к dielectrics have been developed in order to meet the gate stack requirements of III–V MOSFETs [3]. However the introduction of III–V materials into CMOS requires transistor architectures that can take full advantage of the high mobility in the channel, simultaneously neutralising some of the potentially detrimental effects. Among such architectures, the Implant-Free Quantum-Well (IF-QW) transistor [4] offers interesting technological and performance advantages and tradeoffs (Fig. 1.). The IF-QW device features overgrown, heavily doped Source/Drain (S/D) contacts as a replacement of the conventional implanted junctions. The confinement of the carriers in the quantum well in combination with the p-type substrate doping below the channel provides excellent electrostatic integrity.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"23 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Silicon Nanoelectronics Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2010.5562589","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
III–V nMOSFETs are promising candidates for n-channel high-performance transistors in CMOS in the sub-22 nm technology [1]. High electron mobility and low effective mass resulting in a very high injection velocity and low backscattering promise high device performance [2] at a low supply voltage. Various high-к dielectrics have been developed in order to meet the gate stack requirements of III–V MOSFETs [3]. However the introduction of III–V materials into CMOS requires transistor architectures that can take full advantage of the high mobility in the channel, simultaneously neutralising some of the potentially detrimental effects. Among such architectures, the Implant-Free Quantum-Well (IF-QW) transistor [4] offers interesting technological and performance advantages and tradeoffs (Fig. 1.). The IF-QW device features overgrown, heavily doped Source/Drain (S/D) contacts as a replacement of the conventional implanted junctions. The confinement of the carriers in the quantum well in combination with the p-type substrate doping below the channel provides excellent electrostatic integrity.