F. Salgado, T. Gomes, J. Cabral, J. Monteiro, A. Tavares
{"title":"DBTOR: A Dynamic Binary Translation Architecture for Modern Embedded Systems","authors":"F. Salgado, T. Gomes, J. Cabral, J. Monteiro, A. Tavares","doi":"10.1109/ICIT.2019.8755145","DOIUrl":null,"url":null,"abstract":"This article describes a dynamic binary translation (DBT) system specially tailored to fit resource-constrained embedded systems, detailing its design decisions and architectural components. Although designed to support a wide range of low-end architectures, to test its feasibility, we present and evaluate two distinct and widely known source and target architectures, commonly used in embedded systems. The performed evaluations demonstrate legacy Intel MCS-51 code running on a modern Arm v7-M architecture (Cortex-M3) and shows the impact of using DBT techniques on resource-constrained devices.","PeriodicalId":6701,"journal":{"name":"2019 IEEE International Conference on Industrial Technology (ICIT)","volume":"85 1","pages":"1755-1760"},"PeriodicalIF":0.0000,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Industrial Technology (ICIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIT.2019.8755145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This article describes a dynamic binary translation (DBT) system specially tailored to fit resource-constrained embedded systems, detailing its design decisions and architectural components. Although designed to support a wide range of low-end architectures, to test its feasibility, we present and evaluate two distinct and widely known source and target architectures, commonly used in embedded systems. The performed evaluations demonstrate legacy Intel MCS-51 code running on a modern Arm v7-M architecture (Cortex-M3) and shows the impact of using DBT techniques on resource-constrained devices.
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