Multiple Stuck At Fault Diagnosis System For Digital Circuit On FPGA Using Vedic Multiplier and ANN

Abstract

In an electronics circuit, the presence of a Fault leads to undesired or unexpected results. The output of many nodes on the circuit is changed due to the presence of the Fault at one node. So, it is necessary to detect the nature of the Fault present in a particular faulty node. To detect the fault present in the digital circuit, it is necessary to understand logical behavior using mathematical modeling. After the successful modeling, parameters are extracted, and the database is generated. The mathematical model uses Hebbian Artificial Neural Network algorithms [1] [2]. The database generated is used by the fault detection system to find the masked and multiple faults. A fault detection system monitors the faults present in the test circuit and finds the origin and nature of the Fault [3] [4]. The database generated for single stuck-at faults is used to find the multiple faults present in the faulty circuit. In this paper, Modified Vedic Multiplication [5] [4] method is used to optimize the utilization of the proposed system. In this proposed design multiplier of {N x N} bit input and {N} bit output is used, due to which device utilization is decreased, which is the expected outcome from the design. This system is designed using ISE Design Suite and implemented on Spartan-6 FPGA [6] [7].