Implementation of a new coding scheme for improving the SET operations in Phase Change Memory (PCM)

Abstract

Among Non-Volatile Memories (NVMs), PCMs are considered the best alternative to DRAM (dynamic random-access memories). As a result of its superior performance and scalability, there are several advantages over DRAM, including lower leakage and energy consumption, higher cell number, and smaller cells. This kind of memory does, however, suffer from a long write latency. In this article, we present a technique to reduce write latency by reducing the number of SET operations. The proposed method is an improved Write Time Speed-up (WTS) code scheme. In the proposed scheme, a new code based on hamming weight is given, and an appropriate algorithm is written to reduce the number of SET operations. Compared with current methods, the proposed scheme decreased SET and RESET operations by 3.9 percent, SET operations by 3.3 percent, and power consumption by 2.6 percent. Visual Basic 6 and GEM 5 simulations are used to simulate the suggested method