Thawatchai Thongleam, A. Suadet, Arnon Kanjanop, Pratchayaporn Singhanath, Buncha Hirunsing, Weerasak Chuenta, V. Kasemsuwan
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引用次数: 1
Abstract
This paper presents a 0.5 V pseudo fully differential CMOS op-amp with rail-to-rail input/output swing. The circuit is designed based on class AB input and output stages. In the design, quasi FGMOS transistors are employed. The proposed amplifier is designed using 0.18 μm CMOS technology, and the simulation results show rail-to-rail input and output swings. The open-loop gain and gain-bandwidth product show 73.3 dB and 12.6 MHz. The CMRR is 73.2 dB (at 1 kHz) and the power consumption is 27.9 μW.
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