A turbo/MAP decoder for use in satellite circuits

S. Pietrobon
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引用次数: 4

Abstract

The implementation and performance of a turbo/MAP decoder is described. A serial block MAP decoder operating in the logarithm domain is used to obtain a very high performance turbo decoder. Programmable gate arrays and EPROMs allow the decoder to be programmed for almost any code from 4 to 512 states, rate 1/3 to rate 1/7 (higher rates are achieved with puncturing), and interleaver block sizes to 65,536 bits. Seven decoding stages were implemented in parallel. For rate 1/3 and 1/7 16 state codes with an interleaver size of 65,536 bits and operating at up to 356 kbit/s the codec achieved an E/sub b//N/sub 0/ of 0.32 and -0.30 dB, respectively for a BER of 10/sup -5/. BERs down to 10/sup -7/ were also achieved for a small increase in E/sub b//N/sub 0/.
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一种用于卫星电路的turbo/MAP解码器
介绍了一种turbo/MAP解码器的实现和性能。在对数域中使用串行块MAP解码器来获得非常高性能的turbo解码器。可编程门阵列和eprom允许解码器被编程为从4到512状态的几乎任何代码,速率1/3到速率1/7(更高的速率是通过穿刺实现的),交织器块大小为65,536位。七个解码阶段并行实现。对于速率为1/3和1/ 716的状态码,交织器大小为65,536位,工作速度高达356kbit /s,编解码器的E/sub / b//N/sub / 0/分别为0.32和-0.30 dB, BER为10/sup -5/。由于E/sub / b/ N/sub / 0/的小幅增加,ber也降至10/sup -7/。
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