Design for test features of the ARM clock control macro

Abstract

The ability to apply a slow shift clock and an at-speed capture or functional clock is required to keep the average power down during test. A clock control macro (CCM) that can be attached to a PLL has been designed to meet the functional and structural test clocking needs of the Cortextrade-A8 microprocessor core. This includes a glitchless multiplexer, the ability to control separate clocks in isolation and the ability to switch between the reference clock and the PLL VCO clock. This clock control macro is different from previous ARM CCMs in that it has extra capability and it was coded to be synthesizable for reuse.