NTRP: Novel approach for DUT testing based on nonintrusive timing randomization probes using SystemC verification library

Abstract

To meet the rapidly transforming computing requirement of System on Chip (SoC), On-Chip Interconnect BUS specifications is been evolved continuously from single-channel one-way, serial, in-order, shared BUS communication system to complex multi-channel, burst based, out-of-order, separate read/ write/ address BUS communication system. This resulted in development of several industry standard verification methodologies using Hardware Description Languages particularly System Verilog like Universal Verification Methodology (UVM) facilitating constrained randomization based stimulus generation and functional coverage. Adopting such methodologies involves its know-how to get accustomed, recurring licensing charges and simulation overhead. In this work, for stress testing of Design Under Test (DUT), a novel approach is proposed based on Bus Cycle Accurate Nonintrusive Timing Randomization Probes (NTRP) using SystemC Verification (SCV) Library. Based on empirical results, it is argued that the annotations proposed in the work using NTRP causes little overhead, however provides convenient approach for adding timing delays to the interface of DUT including other advantages particularly — transactions reordering for better BUS utilization, selective constrained randomization on interface signal timing, score boarding for self-checking, little simulation overheads and no licensing terms, being based on Open Source SCV, makes it convenient to adopt for DUT testing.