Low-power stack pseudo domino logic using contention-alleviated precharge keeper

Abstract

The dynamic circuits propose superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but these circuits suffer from the degradation of the precharge pulse. Therefore, this article provides different design topologies on the pseudo domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation. The circuit analysis of the power dissipation have been done on Tanner EDA tool for 45 nm technology. The proposed pseudo domino techniques are proffered to economize power dissipation and delay up to 32% and 20% in half adder circuit respectively.