Performance and power trade-offs for cryptographic applications in embedded processors

Abstract

Cryptographic operations are resource-intensive in terms of computational power and energy consumption. Typical approaches towards secure embedded systems employ dedicated modules, such as ASICs, co-processors, and accelerators, to implement these functions and optimize these hardware modules for the adopted algorithms. In our work, we analyze performance and power trade-offs of typical cryptographic algorithms (DES, AES, and RSA) when executed in processing elements that constitute typical embedded processors. Our goal is to characterize and optimize, performance-wise and power-wise, the sources of inefficiency when the encryption/decryption operations are executed in general purpose embedded processors with different processing and caching capabilities. Our analysis focuses on three major parameters: the parallelism of the core (issue width and size of execution window), voltage and frequency switching in the core, and size of the last-level cache (LLC). Those parameters constitute the major power-consumption contributors in all modern embedded general purpose processors. Our results demonstrate that cryptographic operations can be performed efficiently, in terms of both performance and power consumption, for specific values of the analyzed parameters, indicating that reconfigurable approaches can dynamically optimize processor organization and ameliorate the reported performance and power figures in the context of general purpose embedded processors.