On-chip test generation scheme based on reconfigurable programmable and multiple twisted-ring counters

Abstract

Built-in-self-test (BIST) has emerged as a promising solution to VLS I testing problems. The test pattern generation scheme using twisted-ring-counters is more efficient than the pseudo random testing method in detecting random-pattern-resistant faults. Related work based on single fixed-order twisted-ring-counter design requires long test time to achieve high fault coverage and large storage space to store the seeds and the control data. By using multiple programmable twisted-ring-counters (PTRC), a significant reduction in test application cycles were achieved. In this paper, a reconfigurable programmable multiple twisted-ring-counter is proposed to minimize the test time and to generate more number of different test patterns. Here the programmable twisted-ring-counter operates depending on the control signal of the block select module, thus we can generate more number of patterns with less time. The design was modeled in VHDL and simulated using Modelsim SE 6.2 b simulator. Synthesis was done using Xilinx IS E 14.2.