Characterize the DRAM with FPGA

Abstract

Most DRAMs are tested with ATE at laboratory, or SOC at real system environment. ATE is flexible enough to characterize almost all DRAM features, but the price is very high. SOC is low cost, however most times the memory controller features are not open to users. In this paper, FPGA-based DRAM test solutions are surveyed. The study shows now FPGA can test many DRAM internal parameters with the advanced FPGA features. And the flexibility and programmability allow user to fully understand the DRAM characteristics.