Parallel arithmetic expression evaluation on reconfigurable meshes

B. Pradeep , C. Siva Ram Murthy
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引用次数: 4

Abstract

In this paper we present an O(log n) time parallel algorithm for arithmetic expression evaluation, on an n × n processor array with reconfigurable bus system, where n is the sum of the number of operators and constants in the expression. The basic technique involved here is leaves-cutting (rake operation), as in the case of PRAM model algorithms available in the literature for this problem. The input to our algorithm is assumed to be the binary tree associated with a given expression (also known as expression tree with n number of nodes). Our algorithm is faster compared to the previous best time for expression evaluation on mesh connected computers which is O(√n).

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可重构网格的并行算法表达式求值
本文在具有可重构总线系统的n × n处理器阵列上,给出了一种O(log n)时间的算术表达式求值并行算法,其中n为表达式中算子数和常数数之和。这里涉及的基本技术是叶片切割(耙操作),就像文献中可用的PRAM模型算法一样。我们算法的输入假定是与给定表达式(也称为具有n个节点的表达式树)相关联的二叉树。我们的算法比之前在网格连接的计算机上计算表达式的最佳时间(O(√n))要快。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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