Formal methods and automation for system verification

Abstract

Software and hardware systems are growing fast in both functionality and complexity and consequently, the probability of delicate faults existence in these systems is also increasing. Some of these faults may result in disastrous loss in both money and time. One main goal of designing those systems is to construct better and more reliable systems, regardless of the level of their complexity. Formal methods can be used to specify such systems and be automated to verify them. In this paper, we introduce and show how we can use some of those formal methods, Propositional Logic (PL) and First Order Logic (FOL), in specifying and verifying the correctness of related system aspects.