Self-timed full adder designs based on hybrid input encoding

Abstract

Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are described in this paper. While one of the adder designs incorporates redundancy into the logic, the other design does not. Comparisons have been carried out with respect to various self-timed full adder designs which employ only a single widely used delay-insensitive input encoding for both the inputs and outputs. It has been found out from exhaustive simulations that incorporating redundancy into the logic actually benefits in terms of delay, but a non-redundant implementation proves to be beneficial with respect to power and area parameters.