{"title":"The impact of test on reliability, maintainability, and producibility","authors":"G. Nurie","doi":"10.1109/RMCAE.1992.245506","DOIUrl":null,"url":null,"abstract":"High quality ASIC test programs ensure higher reliability and reduced cost of manufacturing and maintenance for the ASICs and for the systems in which they are used. In real world situations of less-than-perfect process yields, test programs with very high fault coverage are necessary for producing defect-free products. Manual test pattern generation is not practical and most conventional automatic test pattern generation cools do not handle sequential circuits. Thus, the designer is forced to adopt design-for-test (DFT) techniques that turn the sequential circuit into a combinational one. However, these DFT techniques cannot be used in leading edge applications where the circuit performance and the logic density cannot be sacrificed. Fortunately, a solution exists that takes advantage of the hierarchical design methodology commonly employed in the design of complex ASICs. This solution automatically produces test patterns for sequential circuits without requiring use of DFT techniques. The Test Design Expert (TDX) from ExperTest, uses an expert-systems approach by utilizing the behavior description of the ASIC to generate the test vectors for faults modeled at the gate level. TDX generates high quality test patterns for sequential circuits, including asynchronous ones, by understanding the function of the circuit from the behavior description written in VHDL. The advantage of this methodology is that the designer does not have to change the design methodology and is not restricted by the constraints of a specific DFT technique. Test development proceeds along with the logic design and no special requirements are imposed on the manufacturing process.<<ETX>>","PeriodicalId":59272,"journal":{"name":"计算机辅助工程","volume":"46 1","pages":"97-101"},"PeriodicalIF":0.0000,"publicationDate":"1992-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"计算机辅助工程","FirstCategoryId":"1087","ListUrlMain":"https://doi.org/10.1109/RMCAE.1992.245506","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
High quality ASIC test programs ensure higher reliability and reduced cost of manufacturing and maintenance for the ASICs and for the systems in which they are used. In real world situations of less-than-perfect process yields, test programs with very high fault coverage are necessary for producing defect-free products. Manual test pattern generation is not practical and most conventional automatic test pattern generation cools do not handle sequential circuits. Thus, the designer is forced to adopt design-for-test (DFT) techniques that turn the sequential circuit into a combinational one. However, these DFT techniques cannot be used in leading edge applications where the circuit performance and the logic density cannot be sacrificed. Fortunately, a solution exists that takes advantage of the hierarchical design methodology commonly employed in the design of complex ASICs. This solution automatically produces test patterns for sequential circuits without requiring use of DFT techniques. The Test Design Expert (TDX) from ExperTest, uses an expert-systems approach by utilizing the behavior description of the ASIC to generate the test vectors for faults modeled at the gate level. TDX generates high quality test patterns for sequential circuits, including asynchronous ones, by understanding the function of the circuit from the behavior description written in VHDL. The advantage of this methodology is that the designer does not have to change the design methodology and is not restricted by the constraints of a specific DFT technique. Test development proceeds along with the logic design and no special requirements are imposed on the manufacturing process.<>