Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS

Abstract

In this paper, two topologies of CMOS low noise amplifiers (LNAs) have been simulated. The inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with ultra low supply voltage, were considered. LNAs were optimized for a GPS/Galileo receiver using UMC 90 nm CMOS technology. Chosen circuits demonstrate a gain of 16.42 dB and 17.27 dB, consuming current 2.492 mA and 3.093 mA, showing NF 1.881 dB and 1.914 dB, third order input interception point (IIP3) −14.99 dBm and −13.3 dBm, input referred 1-dB compression point (Pin-1) −29 dBm and −29.47 dBm for inductively degenerated cascode and folded cascode respectively. Both input return loss (S11) and output return loss (S22) are below −40 dB. For these circuits supply voltage is 0.6 V and die area equals 0.33 mm2.