High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders

T. T. Nguyen-Ly, V. Savin, X. Popon, D. Declercq
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引用次数: 9

Abstract

This paper deals with the recently introduced class of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs). First, optimization results for an extended class of regular NS-FAIDs are presented. They reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose two high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to a baseline Min-Sum decoder, with even better or only slightly degraded decoding performance.
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正则非满射有限字母迭代解码器的高吞吐量FPGA实现
本文讨论了最近引入的一类非满射有限字母表迭代解码器(NS-FAIDs)。首先,给出了一类扩展的正则NS-FAIDs的优化结果。它们揭示了解码性能和硬件实现效率之间可能存在的不同权衡。为了验证优化后的NS-FAIDs在硬件实现方面的优势,我们提出了两种高吞吐量的硬件架构,集成了NS-FAIDs解码内核。实现结果表明,与基线最小和解码器相比,NS-FAIDs在吞吐量和硬件资源消耗方面都有显着改善,解码性能甚至更好或仅略有下降。
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