An energy-efficient switching technique for 2-bit/cycle SAR ADCs

Abstract

A new energy-efficient switching technique for 2bit /cycle successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed switching technique achieves 97.91% less switching energy and 75% less total capacitance over the conventional architecture. A LSB correction method is also proposed to relax the accuracy requirement on the comparator. The prototype was designed in a TSMC 90-nm CMOS process technology. The post-layout simulation results show that the ADC achieves a SNDR of 59.83 dB, power consumption of 0.879 mW and FoM of 10.94 fJ /conversion-step at 100 MHz sampling rate with a 1 V supply voltage.