{"title":"Design of Multifunctional DR Gate and Its Application in ALU Design","authors":"A. G. Rao, A. K. D. Dwivedi","doi":"10.1109/ICIT.2014.49","DOIUrl":null,"url":null,"abstract":"Reversible Logic Technology has emerged as potential logic design style for implementation in Low Power VLSI Design, Quantum Computing and Dissipation less Computing. Based on this technology, a 6×6 Multifunctional Dwivedi - Rao (DR) Gate has been designed for implementation of logical and arithmetical functions. DR gate has been applied for designing of 1-bit ALU to perform NOT, 2 no's NOR, COPIER, ADD, COUT logical and arithmetical operations in one clock cycle. Comparison of various results shows that proposed DR gate and its application in ALU design is better than its counterpart [16] in terms of Quantum Cost, Logical Operations, Worst Case Delay, Garbage output, Total Boolean function performed etc. Proposed gate has been simulated on VHDL and improvement of 72, 40, 24 logical operations on 4, 3, 2 control input signals respectively, without any garbage output.","PeriodicalId":6486,"journal":{"name":"2014 17th International Conference on Computer and Information Technology (ICCIT)","volume":"14 1","pages":"339-344"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 17th International Conference on Computer and Information Technology (ICCIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIT.2014.49","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Reversible Logic Technology has emerged as potential logic design style for implementation in Low Power VLSI Design, Quantum Computing and Dissipation less Computing. Based on this technology, a 6×6 Multifunctional Dwivedi - Rao (DR) Gate has been designed for implementation of logical and arithmetical functions. DR gate has been applied for designing of 1-bit ALU to perform NOT, 2 no's NOR, COPIER, ADD, COUT logical and arithmetical operations in one clock cycle. Comparison of various results shows that proposed DR gate and its application in ALU design is better than its counterpart [16] in terms of Quantum Cost, Logical Operations, Worst Case Delay, Garbage output, Total Boolean function performed etc. Proposed gate has been simulated on VHDL and improvement of 72, 40, 24 logical operations on 4, 3, 2 control input signals respectively, without any garbage output.