Test pattern generation for benchmark circuits using LFSR

Abstract

The test generation problem for circuits is known to be NP-hard. Efficient techniques for test generation are essential in order to reduce the test generation time. Test patterns were generated using ATPG (Automatic Test Pattern Generation) and faults were inserted in the netlist file generated using DFT (Design for Test). Here ATPG is achieved using the combination of Design Compiler and the Tetramax. Fault coverage and test patterns were generated. It was observed that neither a comprehensive functional verification sequence nor a sequence with high stuck-at fault coverage gives high transition fault coverage for sequential circuits. A customized LFSR algorithm is used to find the fault coverage and pattern used to detect the faults. It is found that LFSR techniqque seems to be good when compared to the ATPG tool for the small and medium circuits. LFSR technique yields 100% fault coverage where as Tetramax is giving about 97% fault coverage.