Design of Circuits and Packaging Systems for Security Chips

M. Nagata
{"title":"Design of Circuits and Packaging Systems for Security Chips","authors":"M. Nagata","doi":"10.1587/transele.2022cdi0001","DOIUrl":null,"url":null,"abstract":"SUMMARY Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Pre-ventive measures have been exploited with circuit design and packaging technologies","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"9 1","pages":"345-351"},"PeriodicalIF":0.0000,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEICE Trans. Electron.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1587/transele.2022cdi0001","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

SUMMARY Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Pre-ventive measures have been exploited with circuit design and packaging technologies
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
安全芯片电路与封装系统设计
面向硬件的半导体集成电路(IC)芯片的安全性和可靠性已经得到了很高的要求。本文概述了用于安全应用的IC芯片电路和封装系统的要求和最新发展,特别强调了对物理实现攻击的保护。一旦在硅中实现加密算法,通过芯片前端的电力输送网络(pdn),甚至通过硅衬底的背面,以功率电压变化和电磁波发射的形式,功率侧通道就不希望存在于加密电路中。预防措施已与电路设计和封装技术开发
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Vapor Deposition of Fluoropolymer Thin Films for Antireflection Coating Fundamental Study on Grasping Growth State of Paddy Rice Using Quad-Polarimetric SAR Data Millimeter-Wave Single-Pixel Imaging Using Electrically-Switchable Liquid-Crystal Mask Approaches to High Performance Terahertz-Waves Emitting Devices Utilizing Single Crystals of High Temperature Superconductor Bi2Sr2CaCu2O8+δ Design and Analysis of Si/CaF2 Near-Infrared (λ∼1.7µm) DFB Quantum Cascade Laser for Silicon Photonics
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1