Radix-64 Floating-Point Divider

Abstract

Digit-recurrence division is widely used in actual high-performance microprocessors because it presents a good trade-off in terms of performance, area and power. consumption. In this paper we present a radix-64 divider, providing 6 bits per cycle. To have an affordable implementation, each iteration is composed of three radix-4 iterations; speculation is used between consecutive radix-4 iterations to get a reduced timing. The result is a fast, low-latency floating-point divider, requiring 11, 6, and 4 cycles for double-precision, single-precision and half-precision floating-point division with normalized operands and result. One or two additional cycles are needed in case of subnormal operand(s) or result.