Round-level concurrent error detection applied to Advanced Encryption Standard

Abstract

This paper presents a hardware architecture for online self-test in the context of Advanced Encryption Standard (AES). From the available range of techniques and solutions to be considered for increasing Built In Self-Test (BIST) capabilities, for various reasons - especially due to area requirements - we focused on parity control methods. Therefore, the paper presents a general solution proposing both a basic architecture and a new project designed at the gate level that relies on parity prediction techniques. The contribution brought by our architecture consists of a complete separation between the functional and test channels. The conclusive arguments reveal the proposed architecture as a solution for area reduction; performance and power consumption are also analyzed.