Area optimization in 8T SRAM cell for low power consumption

Abstract

Cache memory plays an important role in high speed electronic devices. SRAM is the key element of cache memory. Cache memory is used for their high speed and SRAM is the element which provides speed to the cache. So this work is mainly concentrated on the simulation and analysis of 8T SRAM cells and their comparative analysis of different parameters such as width to length ratio, capacitance and power consumption. All the simulation has been carried out using Microwind and DSCH2 EDA tool.