On the Relation Between Bit Delay for Slot Reuse and the Number of Address Bits in the Dual-Bus Configuration

O. Sharon
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引用次数: 1

Abstract

In slotted, dual-bus systems, M stations are connected to two unidirectional buses in a linear order and transmissions use slots passing through the stations. If a slot is used by a station i to transmit to a station j, j>i, then the slot can be reused by a station k, k/spl ges/j. We show that the necessary and sufficient length of addresses for full slot reuse is M-2 bits for w=0 and [(M-1)/2/sup w-1/]+w-2 bits for w/spl ges/1 and M>1+2/sup w/, where w is the bit delay at every station.
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双总线配置中槽位复用的位延迟与地址位数的关系
在槽式双母线系统中,M个站点按线性顺序连接到两条单向母线上,传输使用穿过这些站点的槽。如果一个槽位被站i用来向站j, j, >i传输数据,那么这个槽位可以被站k, k/ splges /j重用。我们证明了对于w=0和[(M-1)/2/sup w-1/]来说,完全槽重用的必要和足够的地址长度是M-2位,对于w/spl ges/1和M>1+2/sup w/来说,地址长度是w-2位,其中w是每个站的位延迟。
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