{"title":"On the Relation Between Bit Delay for Slot Reuse and the Number of Address Bits in the Dual-Bus Configuration","authors":"O. Sharon","doi":"10.1109/18.746844","DOIUrl":null,"url":null,"abstract":"In slotted, dual-bus systems, M stations are connected to two unidirectional buses in a linear order and transmissions use slots passing through the stations. If a slot is used by a station i to transmit to a station j, j>i, then the slot can be reused by a station k, k/spl ges/j. We show that the necessary and sufficient length of addresses for full slot reuse is M-2 bits for w=0 and [(M-1)/2/sup w-1/]+w-2 bits for w/spl ges/1 and M>1+2/sup w/, where w is the bit delay at every station.","PeriodicalId":13250,"journal":{"name":"IEEE Trans. Inf. Theory","volume":"32 1","pages":"356-365"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Trans. Inf. Theory","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/18.746844","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In slotted, dual-bus systems, M stations are connected to two unidirectional buses in a linear order and transmissions use slots passing through the stations. If a slot is used by a station i to transmit to a station j, j>i, then the slot can be reused by a station k, k/spl ges/j. We show that the necessary and sufficient length of addresses for full slot reuse is M-2 bits for w=0 and [(M-1)/2/sup w-1/]+w-2 bits for w/spl ges/1 and M>1+2/sup w/, where w is the bit delay at every station.