Fast congestion-aware timing-driven placement for island FPGA

Abstract

A new fast timing-driven placement is presented in this paper, which is partitioning-based method, explicitly considering the congestion for island style FPGAs. The most distinct feature of this approach is that it not only reduces the circuit critical path delay efficiently, but also takes congestion into account. The harmony between partitioning objective and timing improvement goal is kept; moreover, the congestion constraint is added to cost function to improve routability in the meantime. As a result, it avoids the excessive usage of local routing resources while remaining circuit performance much better. The experimental results show our method, FCTP, is very fast. It is able to produce solutions with equal or better routability and up to average 8.19% improvement on performance but only less 1/3 average runtime compared to TVPR [1]. It also achieves much better results than PPFF [7] in terms of timing and congestion with negligible runtime penalty.