High speed FPGA implementation of RSA encryption algorithm

Abstract

In this paper, new structures that implement RSA cryptographic algorithm are presented. These structures are built using a modified Montgomery modular multiplier, where the operations of multiplication and modular reductions are carried out in parallel rather than interleaved as in the traditional Montgomery multiplier. The global broadcast data lines are avoided by interleaving two operations into the same structure, thus making the implementation systolic. The results of implementation in FPGA have shown that the proposed RSA structures outperformed those structures built around a traditional Montgomery multiplier in terms of speed. In terms of area usage, an area-efficient architecture is shown in this paper that has the merit of having a high speed and a reduced area usage when compared with other architectures.