Delay defect diagnosis using segment network faults

Abstract

An objective of delay fault diagnosis is to enable characterization of the source and nature of timing failure in an integrated circuit. However, the most commonly studied defect models (the gate-delay and path-delay fault models) do not adequately capture the complex timing characteristics that a delay fault can exhibit. In this work, we present a novel diagnostic technique that is used to extract an accurate delay fault model we call a segment network fault without the need for any timing information. In our simulation-based experiments, we successfully diagnose delay faults of varying complexity demonstrating the usefulness of the new delay fault model for the purposes of delay defect characterization.