Session 4: Advanced hardware architectures

Abstract

Using hardware architectures to improve performance and energy efficiency has been a key factor for application-specific optimisations. Latest Field Programmable Gate Arrays (FPGA) can not only be used as a reconfigurable hardware platform, they also provide hard core processors and other hard core IPs on the same chip to implement multiprocessor systems on chip, which can be tuned based on the target applications characteristics. In this session, the first two papers present the challenges and optimisations to use hardware architectures based on FPGA for wireless communication systems. In addition an investigation of the crosstalk effects on the Network on Chip energy consumption, as the main interconnection network in multiprocessor systems on chip, is presented.