Extracting the floating gate voltage on the multiple-input FGMOS transistor

Abstract

The extraction of the floating gate voltage on the Multiple-Input Floating-Gate Transistor is discussed in order to understand their behavior in a better way. The lack of linearity at very low voltage is discussed. The presence of a residual charge on the floating gate is experimentally shown despite the use of metal contact to discharge it. This analysis is useful to enhance the mathematical model and consequently to have better results in the simulation process especially when this device is used as an entirely analog processing element. Methods to extract and plot the floating gate voltage are addressed. A comparison between analytical and experimental results is shown.