An efficient Pulse Doppler Radar block level modeling with Xilinx System Generator

Abstract

RADAR (Radio Detection and Ranging) is an electromagnetic device used for detecting and locating objects from their reoccurrence signals. The received signal is then dealt with for information abstraction, like., target detection besides the velocity of the target. In CW radars the frequency measurement is done by de-modulating the received signal with respect to a transmitting. The matching velocity can be anticipated by passing the Doppler spectra through a filter bank. Finding the frequency in a pulse radar system is difficult than in CW radar. Thus, a better approach is the Doppler Processing state machine. The received signal is processed for required information. Detection is done by an algorithm called CFAR (Constant False Alarm Rate). In CFAR, a certain power threshold is determined. If the threshold is too high, then fewer targets are detected and conversely, if the threshold is too low then the false detection rate will increase. This threshold-based algorithm detects false targets in addition to original ones and to overcome this, a method called Cell Averaging Constant False Alarm Rate (CACFAR) would be used. Another parameter velocity is determined by Doppler frequency. The architecture is implemented in MATLAB/SIMULINK using Xilinx System Generator. To implement this model, three processing modules are required. Upon successful simulation, respective Verilog HDL code is generated and that code is run to observe design constraints like area, power, and delay. For CA-CFAR module at 2.5GHz frequency, the On-Chip power is 8.763W. At 0.95V, low On-chip power of 3.932W was observed at the frequency of 4GHz.