Area efficient fully parallel distributed arithmetic architecture for one-dimensional discrete cosine transform

Abstract

The paper describes the design of one-dimensional discrete cosine transform (DCT) which is widely used in image and video compression systems. The objective of this paper is to design an area efficient fully parallel distributed arithmetic (DA) architecture for one-dimensional DCT to be implemented on field programmable gate array (FPGA). DCT requires large amount of mathematical computations including multiplications and accumulations. The multipliers consume increased power and area; hence multipliers are completely discarded in the proposed design. Distributed arithmetic is a method of modification at bit stream for sum of product or vector dot product to hide the multiplications. DA is very much suitable for FPGA designs as it reduces the size of a multiply and accumulate hardware. The speed is increased in the proposed design with the fully parallel approach. In this work, existing DA architecture for 1D-DCT and the proposed area efficient fully parallel DA architecture for 1D-DCT are realized. The simulation is performed using Modelsim6.2b and synthesized with Xilinx IS E Simulator. The 1D-DCT can be extended to 2D-DCT by using row column decomposition technique.