Characterization technique to implement self-timed cells for VLSI design blocks

Abstract

In this article, a methodology to obtain the characterization of the standard cell library called SXLIB is presented, this library is available within Alliance tools. The later proposal is developed based on the spreading analysis that the signal has throughout each cell, this with the objective of obtaining a delay time according to the technology of the manufacture's receiver. This characterization technique can be used with any set of standard cells, for a manufacturing technology that differs by the default one used by Alliance, then, the results of the new characterization are presented of the specified library SXLIB. The importance of knowing the spreading time of the signal, is due to the required time to include the necessary delays in the design of self-timed structures. This is, one of the key phases of the design and synthesis process, expressed in structural language VHDL that generates Alliance tools. Throughout this phase, the designer will prove that the IC works under the desired behavior, in form (logic operation) as in time (maximum and minimum delays, maximum work frequencies, etc.). That is because the obtained results from using the characterized library represent a key point in the design of self-timed structures.