Re-visiting the challenges of programmable concurrent architectures

Abstract

Summary form only given.FPGAs are the most successful example to date of programmable concurrent architectures. The 1980s saw the introduction of several kinds of concurrent processing arrays, ranging from fine-grained FPGAs to systolic arrays, to arrays of microprocessors. Of these, only FPGAs have enjoyed continuous commercial success. Now, however, with the end of the four-decade-old trend towards faster microprocessors, we are witnessing the revival of processor arrays. Due largely to concerns about power consumption multi-core, and indeed many-core architectures, are back at the forefront of system design. It is clear that we have the silicon resources and the circuit design skills to deliver semiconductor devices with highly concurrent programmable architectures and that the aggregate compute power of these arrays is impressive. What is not so straightforward is whether we now have the methodologies and automated tools to efficiently design systems of the complexity demanded by current and future markets. For example, we might enquire whether almost forty years of experience with microprocessors has made us any better prepared for the revival of many-core architectures. Paradoxically, the success of the uni-processor programming model may be the most significant impediment to our future success with highly concurrent, programmable architectures. Or taking an alternative perspective, we might ask whether we can benefit from over 25 years of experience of successfully deploying the programmable concurrency of FPGAs. In this talk, we will re-visit the challenges posed by programmable concurrent architectures and explore some of the assumptions underlying them in an effort to assess the potential of emergent solutions.