Conceptual design of an architecture for hard real time computing

Abstract

The following paper describes efforts to develop a processor architecture that meets the requirements of hard real time computing. The architecture is of the RISC-type with a single, modular CPU. The modules are a Kernel Processor, a Task Processor, a Memory Module and a Controller for internal and external communication. By integrating multiple register files directly accessible by the ALU, the number of main memory accesses decreases and the time for context-switches is reduced considerably. While OS functions, scheduling, time management and interrupt handling are performed by the Kernel Processor, the Task Processor focuses on its primary function, viz., to execute application program code. Assigning the traditionally sequentially performed program-, operating system- and memory-operations to different modules working in parallel results in a significant increase of performance. The reduced instruction set interfacing this architecture allows for a complete and convenient implementation of real time algorithms, especially in distributed systems, without loosing the operational determinism, which was one of the major design guidelines.