{"title":"一个分析模型来估计由于工艺变化导致的PCM失效概率","authors":"Mu-Tien Chang, B. Jacob","doi":"10.1109/SOCC.2011.6085128","DOIUrl":null,"url":null,"abstract":"Phase change memory (PCM) features nonvolatility, high density, and superior power efficiency, making it one of the most promising candidates for future memory systems. This paper studies the impact of process variations on PCM based on a fast analytical model for determining PCM failure probability. The proposed analytical model takes PCM physical dimensions, programming-current amplitude, and programming duration as inputs and produces the corresponding cell resistance. Whether a PCM cell is functional can be determined by comparing the calculated cell resistance with the reference resistance. We further estimate the overall PCM failure probability and demonstrate strategies on how to minimize memory failures. The proposed model thus provides early stage estimation on memory yield.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An analytical model to estimate PCM failure probability due to process variations\",\"authors\":\"Mu-Tien Chang, B. Jacob\",\"doi\":\"10.1109/SOCC.2011.6085128\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Phase change memory (PCM) features nonvolatility, high density, and superior power efficiency, making it one of the most promising candidates for future memory systems. This paper studies the impact of process variations on PCM based on a fast analytical model for determining PCM failure probability. The proposed analytical model takes PCM physical dimensions, programming-current amplitude, and programming duration as inputs and produces the corresponding cell resistance. Whether a PCM cell is functional can be determined by comparing the calculated cell resistance with the reference resistance. We further estimate the overall PCM failure probability and demonstrate strategies on how to minimize memory failures. The proposed model thus provides early stage estimation on memory yield.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085128\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085128","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An analytical model to estimate PCM failure probability due to process variations
Phase change memory (PCM) features nonvolatility, high density, and superior power efficiency, making it one of the most promising candidates for future memory systems. This paper studies the impact of process variations on PCM based on a fast analytical model for determining PCM failure probability. The proposed analytical model takes PCM physical dimensions, programming-current amplitude, and programming duration as inputs and produces the corresponding cell resistance. Whether a PCM cell is functional can be determined by comparing the calculated cell resistance with the reference resistance. We further estimate the overall PCM failure probability and demonstrate strategies on how to minimize memory failures. The proposed model thus provides early stage estimation on memory yield.
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