MIMO-BICM Viterbi解码器的FPGA实现

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005. Pub Date : 1900-01-01 DOI:10.1109/ACSSC.2005.1599849

S. Haene, A. Burg, D. Perels, P. Luethi, N. Felber, W. Fichtner

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引用次数: 17

摘要

研究了多输入多输出(MIMO)无线通信系统中比特交织编码调制(BICM)和单天线编码的Viterbi解码器的FPGA实现。本文介绍了如何将构成电路性能瓶颈的递归添加比较选择(ACS)单元流水线化以提高吞吐量。与采用多个并行解码器相反，硅面积(FPGA上的资源利用率)显着减少。所提出的优化导致在基于IEEE 802.11a的4 × 4 MIMO-WLAN系统原型中实现216 Mbps的吞吐量

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FPGA Implementation of Viterbi Decoders for MIMO-BICM

The FPGA implementation of Viterbi decoders for multiple-input multiple-output (MIMO) wireless communication systems with bit-interleaved coded modulation (BICM) and per-antenna coding is considered. The paper describes how the recursive add-compare-select (ACS) unit, which constitutes the performance bottleneck of the circuit, can be pipelined to increase the throughput. As opposed to employing multiple parallel decoders, silicon area (resource utilization on the FPGA) is significantly reduced. The proposed optimizations lead to an implementation that achieves a throughput of 216 Mbps in a 4 times 4 MIMO-WLAN system prototype based on IEEE 802.11a

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Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.

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