A processing engine for GPS correlation

The correlation process in direct sequence spread spectrum (DSSS) communication systems is key in having successful signal reception. The implementation of real-time correlation in digital signal processors is one of key challenge in the realization of positioning systems today; as a result, most realizations are either application specific integrated circuits (ASIC) or Field Programmable Gate Array (FPGA) based. In this work we have introduced a new correlation engine targeting performance critical Global Positioning Satellite (GPS) based positioning. The processor is based on Reconfigurable Instruction Cell Array (RICA) paradigm. The GPS has been chosen due to its extensive integration in handheld devices (e.g. mobile phones) together with rising energy consumption concerns. We have designed, programmed and implemented several time-domain correlator engines based on RICA architectural paradigm. Various optimization techniques were implemented to adapt the processor to the correlation algorithm and in order to achieve the best performance. 12 and 24 channel correlators are tested using the new processor architecture.