Low power and area SHA-256 hardware accelerator on Virtex-7 FPGA

Lately, there have been many technological developments in communication especially in online transactions, so the demand for highly secure systems and cryptographic algorithms has increased. Cryptographic hash functions are used to protect and authenticate information and transactions. SHA-256 (Secure Hash Algorithm-256) is a one-way hash function characterized by being highly secure and fast while having a high collision resistance. This paper presents a new hardware architecture of SHA-256 with low power consumption and area based on a sequential computation of the message scheduler and the working variables of SHA-256. The hardware was described in HDL and implemented on Virtex-7 FPGA which offers high efficiency and speed. Different optimization techniques were used to further reduce the power and area such as gated clock conversion, arithmetic resource sharing, and structural modeling of small building blocks. The proposed design ran with a maximum frequency of 83.33 MHz. The implementation reports indicated a dynamic power consumption of 13 mW and area utilization of 275 slices while maintaining a good throughput of 0.637 Gbits/s and a relatively high efficiency of 2.32 Mbits/s per slice. Such design with low power and area can be used to hash messages on a portable device opening a whole new area for different applications and opportunities.