FPGA implementation of LMS adaptive filter

Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. This paper aims to combine efficient filter structures with optimized code to create a system-on-chip (SOC) solution for various adaptive filtering problems specially unknown system identification. System identification is one of the most interesting applications for adaptive filters, especially for the Least Mean Square algorithm, due to its strength and calculus simplicity. Based on the error signal, the filter's coefficients are updated and becomes almost exactly as the unknown system' coefficients. Several different adaptive algorithms have been coded in VHDL as well as in MATLAB. The design is evaluated in terms of speed, hardware resources, and power consumption. System identification was mapped into a hardware description language, VHDL. The design was synthesized and implemented using FPGA (Xilinx Spartan3 3s200ft256 kit) with 50 MHz clock.