{"title":"基于数据的低功耗高速加法器预充动态链结构","authors":"W. Paik, In-Chul Hwang, Jae-Wan Kim, S. Kim","doi":"10.1109/ASIC.1997.617000","DOIUrl":null,"url":null,"abstract":"This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the 'precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Data dependent precharging dynamic chain architecture for low power end high speed adders\",\"authors\":\"W. Paik, In-Chul Hwang, Jae-Wan Kim, S. Kim\",\"doi\":\"10.1109/ASIC.1997.617000\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the 'precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617000\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617000","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Data dependent precharging dynamic chain architecture for low power end high speed adders
This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the 'precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.
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